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| N-CHANNEL 100V - 0.030 - 25A DPAK LOW GATE CHARGE STripFETTM II POWER MOSFET TYPE STD25NF10L s s s s s s STD25NF10L VDSS 100 V RDS(on) < 0.035 ID 25 A TYPICAL RDS(on) = 0.030 EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED LOW THRESHOLD DEVICE LOGIC LEVEL DEVICE SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX "T4") 3 1 DPAK TO-252 (Suffix "T4") DESCRIPTION This MOSFET series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced highefficiency, high-frequency isolated DC-DC converters for Telecom and Computer applications. It is also intended for any applications with low gate drive requirements INTERNAL SCHEMATIC DIAGRAM APPLICATIONS s HIGH-EFFICIENCY DC-DC CONVERTERS s UPS AND MOTOR CONTROL ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID(*) ID IDM(*) Ptot dv/dt (1) Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 100 100 16 25 25 100 100 0.67 20 450 -55 to 175 Unit V V V A A A W W/C V/ns mJ C EAS (2) Tstg Tj (*) Pulse width limited by safe operating area. (*) Current Limited by Package February 2003 (1) ISD 25A, di/dt 300A/s, VDD V(BR)DSS, Tj TJMAX (2) Starting T j = 25 oC, ID = 12.5A, VDD = 50V 1/9 STD25NF10L THERMAL DATA Rthj-case Rthj-pcb Tl Thermal Resistance Junction-case Thermal Resistance Junction-pcb(#) Maximum Lead Temperature For Soldering Purpose Max Max 1.5 50 275 C/W C/W C (#) When Mounted on 1 inch2 FR-4 board, 2 oz of Cu. ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating TC = 125C VGS = 16 V Min. 100 1 10 100 Typ. Max. Unit V A A nA ON (*) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V VGS = 4.5 V ID = 250 A ID = 12.5 A ID = 12.5 A Min. 1 0.030 0.035 Typ. Max. 2.5 0.035 0.040 Unit V DYNAMIC Symbol gfs (*) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS = 15 V ID = 12.5 A Min. Typ. 24 1710 250 110 Max. Unit S pF pF pF VDS = 25V f = 1 MHz VGS = 0 2/9 STD25NF10L ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions ID = 12.5 A VDD = 50 V RG = 4.7 VGS = 5 V (Resistive Load, Figure 3) VDD= 80 V ID= 25 A VGS= 5 V Min. Typ. 20 40 38 8.5 21 52 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions ID = 12.5 A VDD = 50 V RG = 4.7, VGS = 5 V (Resistive Load, Figure 3) Min. Typ. 58 20 Max. Unit ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (*) VSD (*) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current 1.5 %. Test Conditions Min. Typ. Max. 25 100 Unit A A V ns nC A ISD = 25 A VGS = 0 88 317 7.2 1.5 di/dt = 100A/s ISD = 25 A VDD = 50 V Tj = 150C (see test circuit, Figure 5) (*)Pulsed: Pulse duration = 300 s, duty cycle (*)Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/9 STD25NF10L Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/9 STD25NF10L Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature . . 5/9 STD25NF10L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STD25NF10L TO-252 (DPAK) MECHANICAL DATA mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 0.6 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 6.4 4.4 9.35 0.8 1 0.023 TYP. MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 6.6 4.6 10.1 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.252 0.173 0.368 0.031 0.039 inch TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.260 0.181 0.397 DIM. H A C2 C DETAIL "A" A1 L2 D DETAIL "A" B = = 3 B2 = = G E 2 L4 1 = = A2 0068772-B 7/9 STD25NF10L 8/9 STD25NF10L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2002 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 9/9 |
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